1. Field of the Invention
The present invention relates to a ferroelectric memory utilizing polarization inversion of ferroelectric substance and a method for accessing the same.
2. Description of the Related Art
Recently there has been active research into large capacity ferroelectric memories. A ferroelectric memory enables high speed access and is nonvolatile, so utilization for a main storage of a portable computer having a file storage and resume function and so on has been expected.
Initial attempts at using a ferroelectric capacitor to store data at a high density used a configuration called a simple matrix type which placed only a capacitor at an intersection of two orthogonal two drive lines (bit line and word line).
FIG. 1 is a circuit diagram of an example of the configuration of a simple matrix type ferroelectric memory.
This simple matrix type ferroelectric memory 1 is configured by a memory cell array 2 comprised of a plurality of (20 in FIG. 1) ferroelectric capacitors FC1 to FC20 arranged in the form of a 4.times.5 matrix, a row decoder 3, and a sense amplifier/column decoder 4.
In the memory cell array 1, one electrode each of the ferroelectric capacitors FC1 to FC5, FC6 to FC10, FC11 to FC15, and FC16 to FC20 arranged in the identical row are connected to identical word lines WL1, WL2, WL3, and WL4, the other electrodes of FC1, FC6, FC11, and FC16 arranged in the identical column are connected to a bit line BL1, the other electrodes of FC2, FC7, FC12, and FC17 are connected to a bit line BL2, the other electrodes of FC3, FC8, FC13, and FC18 are connected to a bit line BL3, the other electrodes of FC4, FC9, FC14, and FC19 are connected to a bit line BL4, and the other electrodes of FC5, FC10, FC15, and FC20 are connected to a bit line BL5.
Further, the word lines WL1 to WL4 are connected to the row decoder 3, and the bit lines BL1 to BL5 are connected to the sense amplifier/column decoder 4.
The ferroelectric capacitor has a hysteresis characteristic and stores and reads data by utilizing this hysteresis characteristic.
Below, an explanation will be made of the hysteresis characteristic of a ferroelectric capacitor In relation to FIGS. 2A to 2C.
FIG. 2A shows the hysteresis characteristic, while FIGS. 2B and 2C show states of the capacitor In which a first data (hereinafter referred to as a data "1") and a second data (hereinafter referred to as a data "0") having inverse phases to each other are written.
The ferroelectric memory is utilized as a nonvolatile memory by defining a state where a plus side voltage is supplied to a ferroelectric capacitor (C in FIG. 2A) and a residual polarization charge of +Qr remains (A in FIG. 2A) as the data "1" and defining a state where a minus side voltage is supplied (D in FIG. 2A) and a residual polarization charge of -Qr remains (B in FIG. 2A) as the data "0" in the hysteresis characteristic shown in FIG. 2A.
Namely in the ferroelectriert memory, the polarizati o n of the ferroelectric film is used for the storage of the data and an electric field is added between the two electrodes configuring the capacitor for reading the data.
Where the field is given in an opposite direction to the polarization, the polarization state direction as that for the polarization, so the data can be read by detecting that difference.
For example, when reading the stored data of a memory cell MC1 in FIG. 1, a predetermined potential difference is given between the bit line BL1 and the word line WL1. By this, the charge stored in the ferroelectric capacitor FC1 is released to the bit line BL1 and the released charge is detected by the sense amplifier of the sense amplifier/column decoder 4.
Summarizing the problem to be solved by the invention, in the case of this simple matrix type ferroelectric memory, since basically no transistor is required for a memory cell, an extremely small memory cell can be realized. In this configuration, however, there is the problem of disturbance as shown below.
For example, when writing the data "1" in the memory cell MC1 (ferroelectric capacitor FC1), 0V is supplied to the word line WL1, and a power supply voltage V.sub.cc is supplied to the bit line BL1.
At this time, the potentials of for example the nonselected word lines WL2 to WL4 are fixed at V.sub.cc /2, but when for example the data "0" is written in the nonselected memory cell MC2 (ferroelectric capacitor FC6), the ferroelectric capacitor FC6 will receive a voltage of V.sub.cc /2, i.e., a so-called disturbance, in the direction in which the data is destroyed.
Accordingly, in a simple matrix type ferroelectric memory, the data of the capacitor for which the nonselection state contin ues for a long t ime gradually deteriorates and finally ends up disappearing. For this reason, the retention of the data could not be guaranteed and this memory was not suited for practical use.
Contrary to this, in U.S. Pat. No. 4,873,664, S. Sheffield et al. solved this problem by arranging a path transistor between the bit line and the capacitor electrode.
As the method for realizing this, a ferroelectric memory employing a method of configuring one memory cell by one path transistor and one ferroelectric capacitor to store one bit (one-transistor+one-capacitor type cell) is shown in FIG. 3.
FIG. 3 is a circuit diagram of an example of the configuration of a folded bit line type ferroelectric memory having a one-transistor+one-capacitor type cell.
This ferroelectric memory 5 is configured by a memory cell array 6 comprising a plurality of (eight In FIG. 3) memory cells MC01 to MC08 arranged in the form of the matrix, a row decoder 7. a plate decoder 8, and sense amplifiers (S/A) 9-1 and 9-2.
Each memory cell MC01 (to MC08) is configured by one path transistor TR01 (to TR08) and one ferroelectric capacitor FC01 (to FC08).
Note that the path transistors TR01 to TR08 are configured by for example n-channel MOS transistors.
Further, one electrode each of the ferroelectric capacitors FC01 and FC03 configuring the memory cells MC01 and MC03 arranged in the identical column are connected via the path transistors TR01 and TR03 to a bit line BL01.
Similarly, one electrode each of the ferroelectric capacitors FC02 and FC04 configuring the memory cells MC02 and MC04 are connected via the path transistors TR02 and TR04 to a bit line BL03, one electrode each of the ferroelectric capacitors FC05 and FC07 configuring the memory cells MC05 and MC07 are connected via the path transistors TR05 and TR07 to a bit line BL02, and one electrode each of the ferroelectric capacitors FC06 and FC08 configuring the memory cells MC06 and MC08 are connected via the path transistors TR06 and TR08 to a bit line BL04.
Further, the other electrodes of the ferroelectric capacitors FC01 and FC02 configuring the memory cells MC01 and MC02 are connected to a common plate line PL01.
Similarly, the other electrodes of the ferroelectrio capacitors FC03 to FC06 configuring the memory cells MC03 and MC06 are connected to a common plate line PL02, and the other electrodes of the ferroelectric capacitors FC07 and FC08 configuring the memory cells MC07 and MC08 are connected to a common plate line PL03.
The gate electrodes of the path transistors TR01 and TR02 configuring the memory cells MC01 and MC02 arranged in the identical row are connected to a common word line WL01.
Similarly, the gate electrodes of the path transistors TR03 and TR04 configuring the memory cells MC03 and MC04 arranged in the identical row are connected to a common word line WL02, the gate electrodes of the path transistors TR05 and TR06 configuring the memory cells MC05 and MC06 arranged in the identical row are connected to a common word line WL03, and the gate electrodes of the path transistors TR07 and TR08 configuring the memory cells MC07 and MC08 arranged in the identical row are connected to a common word line WL04.
A read and write operation of this one-transistor+one-capacitor type cell is carried out by supplying for example a power supply voltage V.sub.cc +.alpha. (.alpha. is a voltage not less than a threshold voltage Vth of the path transistor, for example 1V) to the word line to which the selected memory cell is connected and holding the path transistor TR in a conductive state.
When writing data in for example the memory cell MC01, 0V is supplied to the bit line BL01, and the power supply voltage VCC+1V is supplied to the word line WL01.
By this, the path transistor TR01 becomes the conductive state, and 0V is supplied to one electrode of the ferroelectric capacitor FC01. At this time, the plate line PL01 is held at 0V.
Thereafter, the power supply voltage V.sub.cc is supplied to the plate line PL01, and then 0V is supplied to this. Namely, during the period during which the word line WL01 is held at the power supply voltage V.sub.cc level, a pulse of 0V.fwdarw.V.sub.cc.fwdarw.0V is supplied to the plate line PL01.
By this, polarization occurs at the ferroelectric capacitor FC01, a polarization state from the other electrode (plate line side) to one electrode (bit line side) is exhibited, and the writing is terminated.
Further, when reading the data of the memory cell MC01, 0V is supplied to the bit lines BL01 to BL04, then the lines are left open. Also, at this time, the power supply voltage V.sub.cc +1V is supplied to the word line WL01.
Next, when the potential of the plate line PL01 is raised from 0V to the power supply voltage V.sub.cc level, an amount of charge according to the polarization state of the ferroelectric substance is released to the bit lines BL01 and BL03.
For example, when the polarization state of the ferroelectric capacitor FC01 is the state from the other electrode (plate line side) to one electrode (bit line side), polarization is not inverted. On the other hand, when the polarization state of the ferroelectric capacitor FC01 is the state from one electrode (bit line side) to the other electrode (plate line side), the polarization is inverted.
When inverting the polarization, the movement of charge accompanying the change of the polarization is large compared when not inverting the polarization. Accordingly the potential V1 of the bit line BL01 in the case of inverting the polarization becomes larger than a potential V2 of the bit line BL01 when not inverting the polarization.
Data is read by latching this potential V1 or V2 of the bit line at a level according to its magnitude compared with a reference potential Vref (V1&gt;Vref&gt;V2) by for example a not illustrate dummy cell, that is, V.sub.cc or 0V in the sense amplifier.
Then, by finally supplying 0V to the plate line PL01 again, the polarization inverted ferroelectric capacitor is returned to the original polarization state.
By this, one read operation is completed.
In a ferroelectric memory employing this one-transistor+one-capacitor type cell, it is possible to reduce the frequency of disturbance to zero, but the memory uses one or more transistors for the storage of one bit of data, so there was the problem in that the cell area became large and a reduction of the chip size was difficult.